Wire bonding techniques have been proposed that allow wire bonding on an electrode pad of a semiconductor device in a case where a semiconductor element is formed below the electrode pad. In U.S. Pat. No. 6,261,939 corresponding to JP-A-2003-518739, thicknesses of an interlayer dielectric layer and a wiring layer positioned below the electrode pad is increased to between 1 micrometer (μm) and 2 μm. In JP-A-H8-236706, a wiring layer is multilayered below the electrode pad. Thus, a crack in the layer and a break in the semiconductor element are prevented. In U.S. Pat. No. 5,502,337 corresponding to JP-3432284, a via hole is formed around an electrode pad and not formed below the electrode pad. In US 2005/0258484A1 corresponding to JP-A-2006-5325, a copper (Cu) electrode pad is exposed to an insulation film or a passivation film, and a surface of the copper electrode pad is coated with an aluminum (Al) film. Thus, the copper electrode pad has a large thickness. While protecting the copper electrode pad from corrosion damage, the aluminum film helps reduce a bonding impact force transmitted to lower layers.
However, in the structures of U.S. Pat. No. 6,261,939 and JP-A-H8-236706, it depends on patterns of the layers, whether the crack in the layer and the break in the semiconductor element can be prevented, or not. It has been confirmed that the crack in the layers and the break in the semiconductor element cannot always be prevented. In the structure of U.S. Pat. No. 5,502,337, since the via hole is formed around the electrode pad, drain and source wiring of a power element (i.e., a semiconductor switching element) must be extended accordingly. As a result, an effective length of the wiring is increased, and a wiring resistance and a parasitic inductance of the wiring are increased accordingly. In particular, it is likely that the wiring resistance of the wiring become large, because the wiring become very thin at the lowest layer.
In the structure of US 2005/0258484A1, addition processes are required to form the copper electrode pad coated with the aluminum film. As a result, manufacturing step and cost are increased accordingly. Further, since the copper electrode pad narrows toward its top, a top portion of the copper electrode pad vibrates during wire bonding. Therefore, adhesion of the copper electrode to the semiconductor device is reduced due to the vibration. The vibration may cause cracks in the interlayer dielectric film. Furthermore, the aluminum film on the copper electrode pad is plastically deformed during the wire bonding and pushed off the top portion of the copper electrode pad. As a result, the aluminum film is thinned and cannot suitably reduce the bonding impact force.
One approach to reduce transmission of a bonding impact force to a lower layer is to increase thickness of an upper wiring layer. Lately, multilayered wiring of a semiconductor device is typically formed by a dual-damascene process. In the dual-damascene process, as disclosed, for example, in JP-3403058, a wiring trench and a via trench are formed in an insulation film formed on a semiconductor substrate. A wiring material such as copper (Cu) is filled in the wiring trench and the via trench so an upper wiring layer is connected to a lower wiring layer through a via. Thus, the upper wiring layer and the via are formed in the same step so that time required to form the wiring can be reduced.
FIGS. 21A-21C illustrate a conventional method of forming wiring of a semiconductor device. First, as shown in FIG. 21A, an insulation film 212 is formed on a semiconductor substrate 210 on which a lower wiring layer 211 is formed. Then, a first resist pattern for a via trench 213 is formed by a photolithography process. Then, the insulation film 212 is etched to a predetermined depth by using the resist pattern as a mask. Thus, the via trench 213 is formed.
Then, as shown in FIG. 21B, the insulation film 212 is etched by using a second resist pattern as a mask, until the lower wiring layer 211 is exposed. The second resist pattern is shaped corresponding to the first resist pattern and has a width greater than that of the first resist pattern. Thus, a wiring resist 215 is formed, and the via trench 213 reaches the lower wiring layer 211.
Then, as shown in FIG. 21C, a barrier layer 216 and a seed layer 217 are formed in the via trench 213 and the wiring trench 215. Then, a wiring material is filled in the via trench 213 and the wiring trench 215. The barrier and seed layers 216, 217 prevent the wiring material from diffusing into the insulation film 212. After filling, the excess wiring material is removed by, for example, a chemical mechanical polishing (CMP) process. Thus, a via 218 and an upper wiring layer 219 are formed. For example, the via 218 has a thickness of 1 μm, and the upper wiring layer 219 has a thickness of 1 μm.
In a combined integrated circuit (IC) including a complementary metal-oxide semiconductor (CMOS), a bipolar transistor, and a power element (i.e., semiconductor switching element), there has been a need to increase thickness of an upper wiring layer 219 to absorb a bonding impact force, to improve heat dissipation, or to withstand an increased current of the power element.
To increase the thickness of the upper wiring layer 219, thickness of an insulation film 212 needs to be increased accordingly. However, when the insulation film 212 having increased thickness is formed by using the conventional method illustrated in FIGS. 21A-21C, it is likely that the thickness of the insulation film 212 is nonuniform.
Further, since the amount of etching the insulation film 212 is increased accordingly, it is likely that the depth of the wiring trench 215 is nonuniform. Therefore, the insulation film 212 is over-etched to ensure that the via trench 213 reaches the lower wiring layer 211. If the insulation film 212 is over-etched excessively, the depth of the via trench 213 becomes very small so that the via 218 becomes very thin. As a result, the distance between the lower and upper wiring layers 211, 219 become very small so that a short-circuit may occur due to an increase in a leak current.